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Power Supply DC Characteristics, VDDA = VDDB = VDDQA = VDDQB = 2.1V2.7V, TA = -40☌ to +85☌ QA, QB Outputs Terminated 100 between nQx, Qx VDDQA, VDDQB VDDQA, VDDQB IDDA + IDDB + IDDQA + IDDQB Power Supply DC Characteristics, VDDA = VDDB = VDDQA = VDDQB = 1.8V ±5%, TA = -40☌ to +85☌ Parameter Input Capacitance Input Pull-down Resistor Input Pull-up Resistor Input sink/source, IREF Maximum Junction Temperature, TJ,MAX Storage Temperature, TSTG ESD - Human Body Model ESD - Charged Device Model Item Supply voltage, VDD Inputs, VI Outputs, IO Continuous current Surge current Exposure to absolute maximum rating conditions may affect device reliability. Functional operation of the 8P34S2108 at absolute maximum ratings is not implied. Stresses greater than those listed below can cause permanent damage to the device. NOTE: The absolute maximum ratings are stress ratings only. SELAB Bank B Output Amplitude Selection Table SELAA Bank A Output Amplitude Selection Table See Table 5, DC Input Characteristics, for typical values. Pull-up and pull-down refers to internal input resistors.

Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. LVDS interface levels.Įxposed pad of package. LVDS interface levels.ĭifferential output pair B7. LVDS interface levels.ĭifferential output pair B6. LVDS interface levels.ĭifferential output pair B5. LVDS interface levels.ĭifferential output pair B4. Power supply pin for the channel B outputs QB.ĭifferential output pair B3. LVDS interface levels.ĭifferential output pair B2. LVDS interface levels.ĭifferential output pair B1. LVDS interface levels.ĭifferential output pair B0. LVDS interface levels.ĭifferential output pair A7. LVDS interface levels.ĭifferential output pair A6. Power supply pin for the channel A outputs QA.ĭifferential output pair A5. LVDS interface levels.ĭifferential output pair A4. LVDS interface levels.ĭifferential output pair A3. LVDS interface levels.ĭifferential output pair A2. LVDS interface levels.ĭifferential output pair A1. Power supply pin for the channel A outputs QA. Control input: Output amplitude select for channel A. Non-inverting differential clock/data input. Bias voltage reference for the CLKA, nCLKA input pairs. Power supply pins for the core and inputs of channel A. Power supply pins for the core and inputs of channel B. Bias voltage reference for the CLKB, nCLKB input pairs. Inverting differential clock/data input for channel B. Non-inverting differential clock/data input for channel B. Type Power Input Input Input Output Power Power Output Input Input Input Power Power Output Outputĭescription Power supply ground. Name GND SELAB CLKB nCLKB VREFB VDDB VDDA VREFA nCLKA CLKA SELAA GND VDDQA QA0 nQA0 VDDQA nQA4 QA4 nQA3 QA3 nQA2 QA2 nQA1 QA1 nQA0 QA0 VDDQA

NQB2 QB2 nQB1 QB1 nQB0 QB0 nQA7 QA7 nQA6 QA6 nQA5 QA5 Pin Assignments for 7 × 7 mm 48-VFQFPN Package Top View Lead-free (RoHS 6), 48-lead VFQFPN packaging -40☌ to +85☌ ambient operating temperature Supports case temperature up to +105☌įigure 1.

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(fREF = 156.25MHz, 12kHz 20MHz) Full 1.8V and 2.5V supply voltage mode Low device current consumption (IDD): The integrated bias voltage references enable easy interfacing AC-coupled signals to the device inputs.ĭual 1:8 low skew, low additive jitter LVDS fanout buffers Matched AC characteristics across both channels High isolation between channels Both differential CLKA, nCLKA and CLKB, nCLKB inputsĪccept LVDS, LVPECL and single-ended LVCMOS levels Maximum input clock frequency: 2GHz Output amplitudes: 350mV, 500mV (selectable) Output bank skew: 10ps typical Output skew: 20ps typical Low additive phase jitter, RMS: 45fs typical

The device is characterized to operate from a 1.8V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S2108 ideal for those clock distribution applications demanding well-defined performance and repeatability. AC characteristics such as propagation delay are matched between channels. High isolation between channels minimizes noise coupling. Two independent buffer channels are available, each channel has two low skew outputs. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8P34S2108 is a high-performance, low-power, differential dual 1:8 LVDS output 1.8V/2.5V fanout buffer. REN 8P34S211109 Dual 1:8 LVDS Output 1.8V / 2.5V Fanout Buffer